Asterius uses a distributed bus architecture. Figure 7 shows a schematic of the bus and the various nodes. For redundancy, there are two buses. All components can communicate through both buses, eliminating the possibility of single point failure.
The different components that communicate through the bus are classified into five types based on function: interfaces to other components, housekeeping devices, on-board computers, memory storage devices, housekeeping devices, and the timers.
Many of the instruments use a standard RS-232 serial line interface. Other instruments, especially the high-data-rate instruments, use faster interfaces, such as parallel-line interfaces. Custom built instruments may have their interfaces built directly into their electronics. Components such as actuator motors and rockets are interfaced to the bus by the kinetic controller and monitor unit (KCM unit). The KCM unit sends high-level discrete commands to activate the engines and motors, and then collects telemetry on their status.
The interface to the communications subsystem is more complex than the other interfaces. It must validate and decode the uplinked information before transmitting on the bus. It must also fix simple bit errors. Although the on-board computer could provide this functionality, the communications interface provides it so that Asterius can be controlled even if the computer becomes inoperable for some reason.
Function | Code | Data | Throughput |
---|---|---|---|
(Kwords) | (Kwords) | (KIPS) | |
Command Processing | 1.5 | 6 | 11.5 |
Telemetry Processing | 1.5 | 3.75 | 4.5 |
Autonomy | 22.5 | 15 | 30 |
Fault Monitors | 6 | 1.5 | 22.5 |
Fault Correction | 3 | 15 | 7.5 |
Power Management | 1.8 | 0.75 | 7.5 |
Thermal Control | 1.2 | 2.25 | 4.5 |
Rate Gyro | 1.2 | 0.75 | 13.5 |
Sun Sensor | 0.75 | 0.15 | 1.5 |
Star Tracker | 3 | 22.5 | 3 |
Kinematic Integration | 3 | 0.3 | 22.5 |
Error Determination | 1.5 | 0.15 | 18 |
Thruster Control | 0.9 | 0.6 | 1.8 |
Reaction Wheel Control | 1.5 | 0.45 | 7.5 |
Ephemeris | 5.25 | 3.75 | 6 |
EuropaCam | 2 | 4 | 3 |
Acoustics | 2 | 25 | 40 |
Seismometer | 4.5 | 3.5 | 10 |
Dust Detector | 2 | 2 | 1.5 |
Energetic Particle Detector | 2 | 2 | 1.5 |
Metastable Ionization Det. | 1.5 | 4.5 | 0.5 |
Magnetometer | 0.3 | 0.15 | 1.5 |
MicroWISPCam | 3 | 4 | 2 |
Compression | 8 | 2 | 10 |
Gages | 1.5 | 4 | 3 |
OS Executive | 7 | 4 | 120 |
OS Kernel | 16 | 8 | - |
OS I/O | 4 | 1.4 | 400 |
OS Built-in-tests | 1.4 | 0.8 | 0.5 |
OS Utilities | 2.4 | 0.4 | - |
The computer's baseline throughput is 3.05 million instructions per second, and its baseline memory is 24 megabits (about 15 million 16-bit words). A functional breakdown yielded these numbers. Table 10 lists the memory and throughput estimations for various functions. Because of our ignorance, we can expect the total resources required by launch to be double what the functional breakdown yields. In addition, 30%-50% of the computer's resources should be reserved for spare capacity [3, p. 624]. Therefore, the values yielded by the functional breakdown were multiplied by 4 to obtain the baseline estimate.
The memory requirement of the recorders are determined by the data rate. The period of Europa's rotation is 3.55 days. Asterius can transmit data for a maximum of half that time. Assuming that Asterius can be tracked 40% of the time, and given a data rate of 50 kbps, the total number of bits sent per Europa rotation is 6.134 billion. Assuming that one-third of the data transmitted is collected while Asterius is turned away from the Earth, the required memory to store this data is 2.0448 billion bits. Each recorder would hold one gigabit.
The timer works by raising an interrupt in the on-board computer at regular intervals. (As seen in Figure 7, the timer has a direct connection to the computer: it does not use the bus.) The length of the interval is programmable.
For error recovery, a watchdog circuit is built into the timer. When the timer interrupts the computer, it expects the computer to return an acknowledgment signal. If the timer sends a certain number of interrupt signals without acknowledgment, the watchdog circuit attempts to reset the computer.